Conventional transistors, such as field effect transistors (FETs), typically exhibit a low value of BVdss and a low punch-through voltage. Conventional FETs typically have gates that are formed substantially parallel to the substrates on which they reside. Lightly doped drain (LDD) regions of conventional FETs overlap the gates in planes horizontal to the surfaces of the substrates. Due to this overlap, the breakdown voltage (BVdss) of a conventional FET as measured between an LDD region and the substrate is disadvantageously low.
Previous attempts at compensating for the low BVdss of conventional transistors include increasing the length of spacers so that the overlap between the LDD regions and the gate is minimized. Unfortunately, this technique increases the size of the transistor.
A further drawback of conventional FETs is that it is difficult to control the dopant profile because the dopant profile is in the x-axis direction (parallel to the surface of the substrate). Therefore, conventional approaches typically do not achieve an increased value of BVdss.
Furthermore, conventional approaches exhibit punch-through degradation problems. Conventional approaches additionally increase the size of the transistor in order to maintain a desired channel length in an attempt to minimize the overlap between the LDD regions and the gate in the x-axis direction.
Thus, there is a need in the art for a method of fabricating a transistor, such as an FET, that achieves a desired value of BVdss and a desired punch-through voltage while decreasing the transistor size without compromising channel length.